The integrated circuit industry has, since its inception, maintained a remarkable growth rate by driving increased device functionality at lower cost. One of the primary enabling factors of this growth has been the ability of optical lithography to steadily decrease the smallest feature size that can be formed as part of the integrated circuit pattern. The steady decline in feature size and cost and the corresponding increase in the density of features printed per circuit are commonly referred to as “Moore's Law” or the lithography “roadmap.”
The lithography process involves creating a master image on a mask or reticle (mask and reticle are used interchangeably herein), then projecting an image from the mask onto a resist-covered substrate in order to create a pattern that matches the design intent of defining functional elements, such as transistor gates, contacts, etc., on the device wafer. The more times a master pattern is successfully replicated within the design specifications, the lower the cost per finished device or “chip” will be. Until recently, the mask pattern has been an almost exact duplicate of the desired pattern at the wafer level, with the exception that the mask level pattern may be several times larger than the wafer level pattern, due to an imaging reduction ratio of the exposure tool. The mask pattern is typically formed by depositing and patterning a light-absorbing material on quartz or another transparent substrate. The mask is then placed in an exposure tool known as a “stepper” or “scanner” where light of a specific exposure wavelength is directed through the mask onto the wafers. The light is transmitted through clear areas of the mask, but is attenuated by a desired amount, typically between 90 and 100%, in the areas covered by the absorbing layer. The light that passes through some regions of the mask may also be phase shifted by a desired phase angle, typically an integer multiple of 180 degrees. After being collected by the projection optics of the exposure tool, the resulting aerial image pattern is then focused onto the wafers. A light-sensitive material (photoresist or resist) deposited on the wafer surface interacts with the light to form the desired pattern on the wafer, and the pattern is then transferred into the underlying layers on the wafer to form functional electrical circuits according to well-known processes.
In recent years, the feature sizes being patterned have become significantly smaller than the wavelength of light used to transfer the pattern. This trend towards “sub-wavelength lithography” has resulted in increasing difficulty in maintaining adequate process margins in the lithography process. The aerial images created by the mask and exposure tool lose contrast and sharpness as the ratio of feature size to wavelength decreases. This ratio is quantified by the k1 factor, defined as the numerical aperture of the exposure tool times the minimum feature size divided by the wavelength. There is limited practical flexibility in choosing the exposure wavelength, while the numerical aperture of exposure tools is approaching physical limits. Consequently, the continuous reduction in device feature sizes requires more and more aggressive reduction of the k1 factor in lithographic processes, i.e. imaging at or below the classical resolution limits of an optical imaging system.
Methods to enable low-k1 lithography have used master patterns on the mask that are no longer exact copies of the final wafer level pattern. The mask pattern is often adjusted in terms of the size and placement of features as a function of pattern density or pitch. Other techniques involve the addition or subtraction of extra corners on the mask features (“serifs,” “hammerheads,” and other patterns) and the addition of other geometries that are not intended to be printed on the wafer at all. These non-printing “assist features,” the sole purpose of which is to enhance the printability of the “main features,” may include scattering bars, holes, rings, checkerboards or “zebra stripes” to change the background light intensity (“gray scaling”), and other structures that are well documented in the literature. All of these methods are often referred to collectively as “Optical Proximity Correction” or OPC. With decreasing k1, the magnitude of proximity effects increases dramatically. In current high-end designs, more and more device layers require OPC, and almost every feature edge requires some amount of adjustment in order to ensure that the printed pattern will reasonably resemble the design intent. The implementation and verification of such extensive OPC application is only made possible by detailed full-chip computational lithography process modeling, and the process is generally referred to as model-based OPC. (See “Full-Chip Lithography Simulation and Design Analysis—How OPC Is Changing IC Design,” C. Spence, Proc. SPIE, Vol. 5751, pp. 1-14 (2005) and “Exploring New High Speed, Mask Aware RET Verification Flows,” P. Martin et al., Proc. SPIE 5853, pp. 114-123, (2005)).
The mask may also be altered by the addition of phase-shifting regions which may or may not be replicated on the wafer. A large variety of phase-shifting techniques has been described at length in the literature including alternating aperture shifters, double expose masking processes, multiple phase transitions, and attenuating phase shifting masks. Masks formed by these methods are known as “Phase-Shifting Masks,” or PSMs. All of these techniques to increase the normalized image log slope (NILS) at low k1, including OPC, PSM and others, are referred to collectively as “Resolution Enhancement Technologies,” or RET. The result of all of these RETs, which are often applied to the mask in various combinations, is that the final pattern formed at the wafer level is no longer a simple replicate of the mask level pattern. In fact, it is becoming impossible to simply look at the mask pattern and determine what the final wafer pattern is supposed to look like. This greatly increases the difficulty in verifying that the design data is correct before the mask is made and wafers exposed, as well as verifying that the RETs have been applied correctly and the mask meets its target specifications.
The cost of manufacturing advanced mask sets is steadily increasing. Currently, the cost has already exceeded one million dollars per mask set for an advanced device. In addition, the turn-around time is always a critical concern. As a result, computer simulations of the lithography process, which assist in reducing both the cost and turn-around time, have become an integral part of semiconductor manufacturing. A fast and accurate approach has been described in U.S. Pat. No. 7,003,758, entitled “System and Method for Lithography Simulation,” the subject matter of which is hereby incorporated by reference in its entirety, and is referred to herein as the “lithography simulation system.”
As shown in FIG. 1, a lithography simulation process typically consists of several functional steps. First, a design layout that describes the shapes and sizes of patterns that correspond to functional elements of a semiconductor device, such as diffusion layers, metal traces, contacts, and gates of field-effect transistors, is created. These patterns represent the “design intent” of physical shapes and sizes that need be reproduced on a wafer by the lithography process in order to achieve certain electrical functionality and specifications of the final device.
As described above, numerous modifications to this design layout are required to create the patterns on the mask or reticle used to print the desired structures. A variety of RET methods are applied to the design layout in order to approximate the design intent in the actually printed patterns. The resulting “post-RET” mask layout differs significantly from the “pre-RET” design layout. Both the pre- and post-RET layouts may be provided to the simulation system in a polygon-based hierarchical data file in, e.g., the GDS or the OASIS format.
The actual mask will further differ from the geometrical, idealized, and polygon-based mask layout because of fundamental physical limitations as well as imperfections of the mask manufacturing process. These limitations and imperfections include, e.g., corner rounding due to finite spatial resolution of the mask writing tool, possible line-width biases or offsets, and proximity effects similar to the effects experienced in projection onto the wafer substrate. The true physical properties of the mask may be approximated in a mask model to various degrees of complexity as described in U.S. patent application Ser. No. 11/530,402. Mask-type specific properties, such as attenuation, phase-shifting design, etc., need be captured by the mask model. The lithography simulation system described in U.S. Pat. No. 7,003,758 may, e.g., utilize an image/pixel-based grayscale representation to describe the actual mask properties.
One of the most important inputs to any lithography simulation system is the model for the interaction between the illuminating electric field and the mask. The thin-mask approximation is widely used in most lithography simulation systems. The thin-mask approximation, also called the Kirchhoff boundary condition, assumes that the thickness of the structures on the mask is very small compared with the wavelength and that the widths of the structures on the mask are very large compared with the wavelength. Therefore, the thin-mask approximation assumes the electromagnetic field after mask is the multiplication of the incident field with the mask transmission function. That is, the mask transmits light in an ideal way, different regions on the mask transmit the electric field with the ideal transmittance and phase, and the transition region between different types of structures is a step function. The advantages of the thin-mask model are simple, fast, and reasonably accurate calculations for feature sizes much larger than the source wavelength.
A central part of lithography simulation is the optical model, which simulates the projection and image forming process in the exposure tool. The optical model needs to incorporate critical parameters of the illumination and projection system: numerical aperture and partial coherence settings, illumination wavelength, illuminator source shape, and possibly imperfections of the system such as aberrations or flare. The projection system and various optical effects, e.g., high-NA diffraction, scalar or vector, polarization, and thin-film multiple reflection, may be modeled by transmission cross coefficients (TCCs). The TCCs may be decomposed into convolution kernels, using an eigen-series expansion. For computation speed, the series is usually truncated based on the ranking of eigen-values, resulting in a finite set of kernels. The more kernels are kept, the less error is introduced by the truncation. The lithography simulation system described in U.S. Pat. No. 7,003,758 allows for optical simulations using a very large number of convolution kernels without negative impact on computation time and therefore enables highly accurate optical modeling. (See also “Optimized Hardware and Software for Fast, Full Chip Simulation,” Y. Cao et al., Proc. SPIE Vol. 5754, 407 (2005)).
Further, in order to predict shapes and sizes of structures formed on a substrate, a resist model is used to simulate the effect of projected light interacting with the photosensitive resist layer and the subsequent post-exposure bake (PEB) and development process. A distinction can be made between first-principle simulation approaches that attempt to predict three-dimensional resist structures by evaluating the three-dimensional light distribution in resist, as well as microscopic, physical, or chemical effects such as molecular diffusion and reaction within that layer. On the other hand, all “fast” simulation approaches that may allow full-chip simulation currently restrict themselves to more empirical resist models that employ as an input a two-dimensional aerial image provided by the optical model part of the simulation system. This separation between the optical model and the resist model being coupled by an aerial image is schematically indicated in FIG. 1. For simplicity, optional modeling of further processes, e.g., etch, ion implantation, or similar steps, is omitted.
Finally, the output of the simulation process will provide information on the predicted shapes and sizes of printed features on the wafer, such as predicted critical dimensions (CDs) and contours. Such predictions allow a quantitative evaluation of the lithographic printing process and on whether the process will produce the intended results.
As lithography processes entered below the 65 nm node, 4× reticles for leading-edge chip designs have minimum feature sizes smaller than the wavelength of light used in advanced exposure tools. The thin-mask approximation, however, is very inaccurate at sub-wavelength dimensions where topographic effects (also called thick-mask effects) arising from the vector nature of light become noticeable. These effects include polarization dependence due to the different boundary conditions for the electric and magnetic fields, transmission and phase error in small openings, edge diffraction (or scattering) effects or electromagnetic coupling. (See “Limitation of the Kirchhoff boundary conditions for aerial image simulation in 157 nm optical lithography,” M. S. Yeung and E. Barouch, IEEE Electron Devices Letter, Vol. 21, No. 9, pp. 433-435, (2000) and “Mask topography effects in projection printing of phase-shifting masks,” A. K. Wong and A. R. Neureuther, IEEE Trans. On Electron Devices, Vol. 41, No. 6, pp. 895-902, (1994)). Consequently, resource-consuming rigorous 3D electromagnetic field simulation has become necessary in aerial image formation of a thick-mask, e.g., a PSM mask. However, software that implements such rigorous 3D electromagnetic field simulation often runs extremely slow and hence is limited to extremely small areas of a chip design layout (on the order of a few square microns). Software tools in this category include “SOLID-E” from Sigma-E (Santa Clara, Calif., USA), “Prolith” from KLA-Tencor (San Jose, Calif., USA), and “EM-Suite” from Panoramic Technology (San Francisco, Calif., USA). These software tools are not viable for full-chip lithography modeling. Some efforts have been made to address mask 3D effects recently for full-chip lithography modeling. Two major approaches in the literature are the domain decomposition method (DDM) and the boundary layer model (BLM). (See “Simplified Models for EDGE Transitions in Rigorous Mask Modeling,” K. Adam, A. R. Neureuther, Proc. of SPIE, Vol. 4346, pp. 331-344, (2001) and “Boundary Layer Model to Account for Thick Mask Effects in PhotoLithography,” J. Tirapu-Azpiroz, P. Burchard, and E. Yablonovitch, Optical Microlithography XVI, Anthony Yen, Ed., Proc. of SPIE, Vol. 5040, pp. 1611-1619, (2003)).
The DDM is based on the idea that the near field characteristics of complex masks are equivalent to the superposition of the diffraction of other masks that comprised the original mask. A particular form of DDM, the edge-DDM, includes three steps. First, all types of edge structures that will be encountered in any mask design data are identified and for each edge structure, an electromagnetic spectrum is simulated using one of the existing rigorous 2D algorithms, e.g., Finite-Discrete-Time-Domain (FDTD) or Rigorous Coupled-Waveguide Analysis (RCWA), to generated a library. Next, original mask design data are decomposed into a set of edge structures and its corresponding electromagnetic spectrum is selected from the pre-simulated library. Finally, all selected spectra are combined based on the decomposition information to form a synthesized, approximate near electric field distribution for the original mask design data. The main advantage of edge-DDM is that it provides a simple method to simulate any arbitrary, “Manhattan” structure to an accuracy level equal to rigorous thick mask simulations with a speed that can be extended to full chip mask calculations. There are, however, two major limitations with implementing edge-DDM. First, electromagnetic cross-talk between adjacent and connecting edges will grow as mask dimension continue to shrink. These nonlinear cross-talking effects cannot be taken into account by edge-DDM because the mask structure can no longer be treated as linear combinations of scattering effects from isolated edge components. The other problem is that more high scattered orders will be collected by the imaging system when both high angle off-axis illumination and larger numerical apertures are utilized for mask inspection. (See “Domain decomposition methods for simulation of printing and inspection of phase defects,” M. Lam, K. Adam, and A. Neureuther, Optical Microlithography XVI, Anthony Yen, Ed., Proc. of SPIE, Vol. 5040, pp. 1492-1501, (2003)).
Alternatively, Tirapu-Azpiroz et al. proposed the boundary layer model to alternating phase-shifting masks by adding local perturbations (in the form of local rectangular functions with adjustable width, transmission and phase) near the edges of the phase shifting region. Bai has applied the boundary layer model to effectively approximate the 3D mask effect of alternating aperture phase-shifting mask (AAPSM). (See “Approximation of Three Dimensional Mask Effects with Two Dimensional Features,” M. Bai, et al., Emerging Lithographic Technologies IX, R. Scott Mackay, Ed., Proc. SPIE, Vol. 5751, pp. 446-454, (2005)). Unlike the models relying simply on the thin-mask model, the boundary layer model incorporates topographic effects and polarization dependencies of the field transmitted by the mask and can account for nonlinear interaction effects from nearby edges. It is almost a complete empirical approach, with no first-principle components and every parameter of the boundary layer structure is based on calibration of a particular mask structure that the boundary layer is attached to.
While both methods have demonstrated some successes, their disadvantages, such as inability to take into account cross-talking effects or inability to systematically generate a mask 3D model, have limited their use to more general mask features. Furthermore, both methods are either polygon-based or edge-based approaches that are not suitable for implementing into a high-speed parallel image computing system, such as the system described in U.S. Pat. No. 7,003,758. As a result, there exists a strong need for methods to create a very fast and very accurate imaging-based 3D mask model that includes mask polarization and edge scattering effects as well as supports partially polarized illumination. Such an imaging-based 3D mask model should be easily implemented into a full-chip lithography simulation system, such as the one described in U.S. Pat. No. 7,003,758.